SH7265 Datasheet, PDF (1418/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 AT Attachment Packet Interface (ATAPI)
(4) PIO timing register (ATAPI_PIO_TIMING)
Before accessing an ATAPI device, set the number of machine cycles in the following bits in this
register.
A machine cycle is equal to an enhanced bus clock cycle. Its frequency is the same as of the bus
clock.
Bit: 31
-
Initial value: ^-
R/W: R
Bit: 15
-
Initial value: -
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
pSDCT
pSDPW
pSDST
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
pMDCT
pMDPW
pMDST
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31, 30 

R Reserved
29 to 24 pSDCT
000000 R/W These bits specify the cycle time for a slave ATAPI
device.
23 to 19 pSDPW
00000
R/W These bits specify the width of the IDEIORD#/IDEIOWR#
pulse for a slave ATAPI device.
18 to 16 pSDST
000
R/W These bits specify the address setup time for
IDEIORD#/IDEIOWR# for a slave ATAPI device in PIO
mode.
15, 14 

R Reserved
13 to 8 pMDCT
000000 R/W These bits specify the cycle time for the master ATAPI
device.
7 to 3 pMDPW
00000
R/W These bits specify the width of the IDEIORD#/IDEIOWR#
pulse for the master ATAPI device.
2 to 0 pMDST 000
R/W These bits specify the address setup time for
IDEIORD#/IDEIOWR# for the master ATAPI device in
PIO mode.
Note: The prefix pS pertains to slaves, and pM, to the master.
Rev. 1.00 Mar. 14, 2008 Page 1382 of 1984
REJ09B0351-0100