SH7265 Datasheet, PDF (1442/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
Setting values of the SB_STEN and SA_STEN bits for blit operations are shown below.
Table 28.3 Settings of the SB_STEN and SA_STEN Bits and Blit Operations
SB_STEN
0
1
SA_STEN
0
1
0
1
Waiting mode
Setting is prohibited. Blitting does not proceed.
Blitting is enabled but only for Source B.
Blitting is enabled for both Source A and Source B.
• Blit operations only for source SA alone are not possible. If only a single source signal is
supplied, use source SB.
• If the value 0 is written to during blitting, the operation is ended forcibly.
• The value "1" should never be written to these bits when neither buffer SA nor buffer SB is
empty. Whether the buffers are empty or not is checked by the state of the GR_DOSTAT
register.
• When both of the bits SB_STEN and SA_STEN are set to 1, blit operation only proceeds when
the same amounts of data are to be transferred from buffers SA and SB (for details, see section
28.4.3 (2), Summary of Operations between the Blitter and External Memory.)
Rev. 1.00 Mar. 14, 2008 Page 1406 of 1984
REJ09B0351-0100