SH7265 Datasheet, PDF (483/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.8 Determination of DMA Channel Priorities
11.8.1 Channel Priorities
Channel 0 has the highest priority. The priorities of channels are fixed in the following order:
Channel 0 > channel 1 > channel 2 > … > channel 12 > channel 13
11.8.2 Operation at Occurrence of Multiple DMA Requests
The DMAC determines DMA channel priorities per single operand transfer.
If a DMA request with a higher channel priority occurs during operand transfer on one channel,
operand transfer on the higher-priority channel is started after operand transfer on the current
channel has ended. Figure 11.11 shows an example of DMAC outline operation when multiple
DMA requests occur. The thick lines in figure 11.11 indicate the period during which DMA
request signals are at a low level (channel 0 (ch0), channel 2 (ch2), and channel 3 (ch3) are set to a
level sense and channel 1 (ch1) is set to an edge sense).
• Transfer on channel 3 is started because DMA requests are assumed to be non-existent in
channel 2 because channel 2 is during the mask period.
• Transfer on channel 0 is started because this channel has the highest channel priority.
• Transfer on channel 2 is started because this channel has the highest channel priority at this
point.
• Transfer on channel 3 is started because there are no other requests at this point.
• If DMA requests for channel 0, channel 1, and channel 3 occur at the same time, transfer on
channel 0 is started because channel 0 has the highest priority.
• When transfer on channel 0 ends, transfer on channel 1 is started because channel 1 has the
second highest priority.
• If a DMA request (low or high level request edge) occurs during DMA transfer on channel 1,
DMA transfer on channel 1 is started again after DMA transfer on channel 1 ends. If an edge
sense is set, no mask period exists.
• When DMA transfer on channel 1 ends, DMA transfer on channel 3 is started because there is
no other transfer request.
• When channel 3 is during the mask period, DMA transfer is not started because there is no
other transfer request. DMA transfer on channel 3 is started after the mask period ends.
Rev. 1.00 Mar. 14, 2008 Page 447 of 1984
REJ09B0351-0100