SH7265 Datasheet, PDF (665/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data after write.
Figure 12.102 shows the timing in this case.
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 12.102 Contention between Buffer Register Write and Compare Match
Rev. 1.00 Mar. 14, 2008 Page 629 of 1984
REJ09B0351-0100