SH7265 Datasheet, PDF (1696/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
1
RAME1 1
R/W RAM Enable 1 (page 1 of high-speed on-chip RAM0*)
0: Access to page 1 is disabled.
1: Access to page 1 is enabled.
0
RAME0 1
R/W RAM Enable 0 (page 0 of high-speed on-chip RAM0*)
0: Access to page 0 is disabled.
1: Access to page 0 is enabled.
Note: * For the addresses of each page, see section 32, On-Chip RAM.
33.2.9 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables writing from CPU0 to each
page of the high-speed on-chip RAM0.
Setting the RAMWEn (n = 0 to 3) bit in SYSCR2 to 1 enables writing to page n. When the
RAMWEn bit is cleared to 0, writing to page n is ignored. The initial value of the RAMWEn bit is
1.
When clearing the RAMWEn bit to 0, be sure to execute an instruction to read from and write to
the same arbitrary address in page n before setting the RAMWEn bit. If not executed, the data last
written to page n may not be written to the high-speed on-chip RAM.
Set SYSCR2 using the program that is placed in a space other than the high-speed on-chip RAM
space. Furthermore, an instruction to read SYSCR2 should be located immediately after the
instruction to write to SYSCR2. Otherwise, normal access to the high-speed on-chip RAM is not
guaranteed.
Note: When writing to this register, see section 33.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RAM RAM RAM RAM
WE3 WE2 WE1 WE0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Rev. 1.00 Mar. 14, 2008 Page 1660 of 1984
REJ09B0351-0100