SH7265 Datasheet, PDF (1386/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.24 FIFO Port Access Categorized by Pipe
Pipe
DCP
PIPE1 to PIPE7
Access Method
CPU access
CPU access
DMA access
Port that can be Used
CFIFO port register
CFIFO port register
D0FIFO/D1FIFO port register
D0FIFO/D1FIFO port register
(b) Method of Reading Partial Data from FIFO ports
In reading data form an FIFO port when the width of the data to be read is shorter than the bit
width set by the MBW bits in the FIFO port select register, read the bit width specified by the
MBW bits and use software to discard the unnecessary portion of the data.
In writing data form an FIFO port when the width of the data to be written is shorter than the bit
width set by the MBW bits in the FIFO port select register, proceed with access as shown in the
examples below. These examples show ways of writing 24-bit data when the width for access to
the FIFO port has been set to 32 bits (MBW = 10).
Example 1 of writing partial data: Writing data with 16-and 8-bit widths once each
Start
[1]
Set MBW to 01
[2] ^{Write the data for 16-bit to the}
FIFO port register
[3]
Set MBW to 00
[4] ^{Write the data for 8-bit to the}
FIFO port register
[1] Set FIFO port access bit width to 16-bit.
[2] When setting the BIGEND bit to 1, write to bits 31 to 16.
When clearing the BIGEND bit to 0, write to bits 15 to 0.
[3] Set FIFO port access bit width to 8-bit.
[4] When setting the BIGEND bit to 1, write to bits 31 to 24.
When clearing the BIGEND bit to 0, write to bits 7 to 0.
Writing ends
Figure 25.10 Example 1 of Writing Partial Data to an FIFO Port
Rev. 1.00 Mar. 14, 2008 Page 1350 of 1984
REJ09B0351-0100