SH7265 Datasheet, PDF (1519/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
Graphic planes P1 and P2
expanded in the SDRAM
Processing in the blitter
Graphic plane PX
expanded in the SDRAM
Starting address of the
P1 area (Word address) ^{P1 read area SSWIDH}
(Number of pixels)
Target P1 area
P1 read area
SSHIGH
(Number of lines)
DMA
transfer
for n times
Blitter
Background plane
Line pitch (64-byte boundary)
Starting address of the
P2 area (Word address)
P2 read area SSWIDH
(Number of pixels)
Target P2 area
DMA
transfer
for n times
SA
buffer
Blending
in the blitter
in units of data
written to the
input buffer
SB
buffer
P2 read area
SSHIGH
(Number of lines)
A
B
Front plane
Line pitch (64-byte boundary)
Basic procedure for graphics processing
1. The CPU controls the various DMA source/destination settings for transferring
the graphics-related data in the SDRAM to the 2DG.
2. Data to be processed in the graphics block is written to the input buffer by DMA.
3. Blitter operation is processed in units of the data written in the input buffer, and
the processed data is stored in the output buffer.
4. Receiving the transfer request from the output buffer, the CPU starts the DMA to
transfer the processed data to the SDRAM memory space.
Resizing
DC
buffer
DMA
transfer
for n times
Starting address of the
PX area (Word address) ^{PX read area DCWIDH}
(Number of pixels)
PX write area
DCHIGH
(Number of lines)
Target PX area
A
B
Line pitch (64-byte boundary)
Figure 28.20 Summary of Blitter Operations
Rev. 1.00 Mar. 14, 2008 Page 1483 of 1984
REJ09B0351-0100