SH7265 Datasheet, PDF (1598/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3.22 Forcibly-Transferred Stream Data Byte Amount Indicating Register (SDBTR)
SDBTR is a 32-bit readable register that indicates the amount of data stored in the DOUT_RAM
in terms of bytes when the PUSH bit in SDFOR is set.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PUSHBYTE[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 16 
15 to 0 PUSHBYTE
[15:0]
Initial
Value R/W
All 0 R
H'0000 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Amount of Forcibly Transferred Data Stored in
DOUT_RAM
These bits indicate the amount of data stored in the
DOUT_RAM to be transferred forcibly in terms of
bytes.
Rev. 1.00 Mar. 14, 2008 Page 1562 of 1984
REJ09B0351-0100