SH7265 Datasheet, PDF (1592/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3.11 Audio Processing Information Setting Register (ADIFR)
ADIFR is a 32-bit readable/writable register that sets the sampling frequency and bit rate
information. (Note that 128 kbps/channel = 256 kbps in stereo is only settable.)
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
SFB[5:0]
-
BR[2:0]
SF[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 17 
16
REV
15, 14 
13 to 8 SFB[5:0]
7

6 to 4 BR[2:0]
Initial
Value R/W
All 0 R
0
R/W
All 0 R
000000 R/W
0
R
000
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
ADIFR Setting-Predetermined 2
This bit should be set to 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
ADIFR Setting-Predetermined 1
The following value should be specified for bit rate
setting:
110000: 128 kbps/channel (→ 256 kbps in stereo)
Reserved
This bit is always read as 0. The write value should
always be 0.
Bit Rate
These bits set the bit rate for one channel.
100: 128 kbps/channel (→ 256 kbps in stereo)
Rev. 1.00 Mar. 14, 2008 Page 1556 of 1984
REJ09B0351-0100