SH7265 Datasheet, PDF (2010/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Compare match timer (CMT) ................. 673
Complementary PWM mode .................. 565
Configuration of RCAN-TL1 ............... 1005
Conflict between byte-write and
count-up processes of CMCNT .............. 684
Conflict between word-write and
count-up processes of CMCNT .............. 683
Conflict between write and
compare-match processes of CMCNT.... 682
Conflict error .......................................... 832
Control signal timing ............................ 1882
Control transfer stage transition
interrupt ................................................ 1340
Control transfers when the function
controller function is selected............... 1358
Control transfers when the host
controller function is selected............... 1357
Controller area network (RCAN-TL1) ... 929
CPU .......................................................... 47
Crystal oscillator..................................... 117
Cycle-stealing transfer mode .................. 425
D
D/A converter (DAC) ........................... 1129
D/A converter characteristics ............... 1960
D/A output hold function in software
standby mode........................................ 1135
Data array ....................................... 246, 261
Data format in registers ............................ 52
Data formats in memory ........................... 52
Data transfer instructions.......................... 73
DC characteristics................................. 1867
Definitions of A/D conversion
accuracy................................................ 1124
Delayed branch instructions ..................... 55
Denormalized numbers............................. 98
Determination of DMA channel
priorities.................................................. 447
Device state transition interrupt............ 1338
Rev. 1.00 Mar. 14, 2008 Page 1974 of 1984
REJ09B0351-0100
Direct memory access controller
(DMAC).................................................. 363
Displacement accessing ............................ 57
Divider 1 ................................................. 117
Divider 2 ................................................. 117
DMA activation ...................................... 430
DMA requests ......................................... 442
DMAC activation.................................... 612
DMAC interface ................................... 1029
DMAC timing ....................................... 1899
Dual-processor active state ....................... 91
E
ECC error check.................................... 1182
Effective address calculation .................... 58
Electrical characteristics ....................... 1865
Equation for getting SCBRR value......... 755
Example of time triggered system ........ 1020
Exception handling ................................. 137
Exception handling vector table.............. 141
Exception source generation
immediately after delayed branch
instruction ............................................... 157
Exceptions triggered by instructions....... 153
External trigger input timing................. 1122
F
FIFO buffer........................................... 1346
FLCTL interrupt requests ..................... 1189
FLCTL timing....................................... 1913
Floating-point operation instructions ........ 85
Floating-point ranges ................................ 96
Floating-point registers ............................. 99
Floating-point unit (FPU) ......................... 93
Flow of the user break operation............. 236
Format of double-precision
floating-point number ............................... 94