SH7265 Datasheet, PDF (1488/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
5. MVON should be set to 1 before EXTEN in GR_MIXPLY is set to 1. When MVON = 0,
setting EXTEN in GR_MIXPLY to 1 is prohibited.
6. Follow the procedure below when using the MVON bit to switch VSYNC between
external and internal synchronization.
(1) Set the GR_MIXPLY register to disable display.
(2) Change the MVON bit to change the synchronization of VSYNC.
(3) At least twice, check that VSYNC is being generated after the change.
(4) Set the GR_MIXPLY register to enable display.
Table 28.6 FCFD Bit Details
FCFD
(Register Value) Fc
Fd
Remarks
000 (Initial value) 1
1 - αdc SE buffer input image is premultiplied
001
αdc
1 - αdc SE buffer input image is non-premultiplied
010
1
0
Only the graphics are output
011
0
1
Only the moving pictures are output.
100
0
0
Nothing is output (Black screen output)
Others


Reserved
Note:
The FCFD bits are set automatically by the hardware according to the GR_MIXPLY settings
as follows, however, the FCFD bit is not changed:
When only the externally supplied moving picture is selected (OUTEN = 0, EXTEN = 1):
FCFD = 011
When only the graphic image is selected (OUTEN = 1, EXTEN = 0): FCFD = 010
When display is prohibited (OUTEN = 0, EXTEN = 0): FCFD = 100
Rev. 1.00 Mar. 14, 2008 Page 1452 of 1984
REJ09B0351-0100