SH7265 Datasheet, PDF (23/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

19.3.2 Status Register (SSISR) .................................................................................... 897
19.3.3 Transmit Data Register (SSITDR).................................................................... 901
19.3.4 Receive Data Register (SSIRDR) ..................................................................... 901
19.3.5 FIFO Control Register (SSIFCR) ..................................................................... 902
19.3.6 FIFO Status Register (SSIFSR) ........................................................................ 905
19.3.7 FIFO Data Register (SSIFDR).......................................................................... 908
19.4 Operation Description....................................................................................................... 909
19.4.1 Bus Format........................................................................................................ 909
19.4.2 Non-Compressed Modes................................................................................... 910
19.4.3 Operation Modes............................................................................................... 920
19.4.4 Transmit Operation ........................................................................................... 921
19.4.5 Receive Operation............................................................................................. 924
19.4.6 Serial Bit Clock Control.................................................................................... 927
19.5 Usage Notes ...................................................................................................................... 928
19.5.1 Limitations from Overflow during Receive DMA Operation........................... 928
19.5.2 Note on Using Oversampling Clock ................................................................. 928
Section 20 Controller Area Network (RCAN-TL1) ..........................................929
20.1 Summary........................................................................................................................... 929
20.1.1 Overview........................................................................................................... 929
20.1.2 Scope................................................................................................................. 929
20.1.3 Audience ........................................................................................................... 929
20.1.4 References......................................................................................................... 929
20.1.5 Features............................................................................................................. 930
20.2 Architecture ...................................................................................................................... 931
20.3 Programming ModelOverview ..................................................................................... 934
20.3.1 Memory Map .................................................................................................... 934
20.3.2 Mailbox Structure ............................................................................................. 936
20.3.3 RCAN-TL1 Control Registers .......................................................................... 953
20.3.4 RCAN-TL1 Mailbox Registers......................................................................... 974
20.3.5 Timer Registers................................................................................................. 989
20.4 Application Note............................................................................................................. 1003
20.4.1 Test Mode Settings ......................................................................................... 1003
20.4.2 Configuration of RCAN-TL1 ......................................................................... 1005
20.4.3 Message Transmission Sequence.................................................................... 1010
20.4.4 Message Receive Sequence ............................................................................ 1024
20.4.5 Reconfiguration of Mailbox............................................................................ 1026
20.5 Interrupt Sources............................................................................................................. 1028
20.6 DMAC Interface ............................................................................................................. 1029
20.7 CAN Bus Interface.......................................................................................................... 1030
Rev. 1.00 Mar. 14, 2008 Page xxiii of xxxvi