SH7265 Datasheet, PDF (28/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

25.3.29 USB Request Value Register (USBVAL) ...................................................... 1277
25.3.30 USB Request Index Register (USBINDX) ..................................................... 1278
25.3.31 USB Request Length Register (USBLENG) .................................................. 1279
25.3.32 DCP Configuration Register (DCPCFG)........................................................ 1280
25.3.33 DCP Maximum Packet Size Register (DCPMAXP) ...................................... 1281
25.3.34 DCP Control Register (DCPCTR) .................................................................. 1282
25.3.35 Pipe Window Select Register (PIPESEL)....................................................... 1291
25.3.36 Pipe Configuration Register (PIPECFG) ........................................................ 1292
25.3.37 Pipe Buffer Setting Register (PIPEBUF)........................................................ 1297
25.3.38 Pipe Maximum Packet Size Register (PIPEMAXP)....................................... 1299
25.3.39 Pipe Timing Control Register (PIPEPERI)..................................................... 1301
25.3.40 PIPEn Control Registers (PIPEnCTR) (n = 1 to 5)......................................... 1306
25.3.41 PIPEn Control Registers (PIPEnCTR) (n = 6 to 9)......................................... 1317
25.3.42 Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5).................... 1322
25.3.43 Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) ............................... 1324
25.3.44 Device Address Configuration Registers (DEVADDn) (n = 0 to 9, A).......... 1326
25.3.45 USB AC Characteristics Switching Register 0 (USBACSWR0).................... 1329
25.3.46 USB AC Characteristics Switching Register 1 (USBACSWR1).................... 1330
25.4 Operation ........................................................................................................................ 1331
25.4.1 System Control ............................................................................................... 1331
25.4.2 Interrupt Functions.......................................................................................... 1333
25.4.3 Pipe Control .................................................................................................... 1342
25.4.4 FIFO Buffer .................................................................................................... 1346
25.4.5 Control Transfers (DCP)................................................................................. 1357
25.4.6 Bulk Transfers (PIPE1 to PIPE5) ................................................................... 1360
25.4.7 Interrupt Transfers (PIPE6 to PIPE9) ............................................................. 1360
25.4.8 Isochronous Transfers (PIPE1 and PIPE2) ..................................................... 1362
25.4.9 SOF Interpolation Function ............................................................................ 1367
25.5 Usage Notes .................................................................................................................... 1368
25.5.1 Procedure for Setting the USB Transceiver .................................................... 1368
Section 26 SD Host Interface (SDHI) ............................................................. 1369
Section 27 AT Attachment Packet Interface (ATAPI).................................... 1371
27.1 Features........................................................................................................................... 1371
27.2 Input/Output Pins............................................................................................................ 1372
27.3 Register Description ....................................................................................................... 1373
27.3.1 ATAPI Interface Registers.............................................................................. 1373
27.3.2 ATAPI Interface Control Register Map.......................................................... 1376
27.4 Operation ........................................................................................................................ 1391
Rev. 1.00 Mar. 14, 2008 Page xxviii of xxxvi