SH7265 Datasheet, PDF (2009/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Index
Numerics
16-bit/32-bit displacement ........................ 57
2D Graphics Engine (2DG) .................. 1399
2DG timing ........................................... 1951
A
A/D conversion time
(multi mode and scan mode)................. 1122
A/D conversion time (single mode)...... 1121
A/D conversion timing ......................... 1121
A/D converter (ADC) ........................... 1103
A/D converter activation......................... 612
A/D converter characteristics................ 1959
A/D converter start request delaying
function................................................... 605
A/D trigger input timing ....................... 1912
Absolute address....................................... 57
Absolute address accessing....................... 57
Absolute maximum ratings................... 1865
AC characteristics................................. 1877
AC characteristics measurement
conditions ............................................. 1958
Accessing CS space ................................ 304
Accessing SDRAM................................. 318
Address array.................................. 246, 260
Address errors......................................... 147
Address map ........................................... 269
Addressing modes..................................... 58
AESOP ................................................. 1545
Analog input pin ratings ....................... 1127
AND/NAND flash memory controller
(FLCTL) ............................................... 1137
Arithmetic operation instructions ............. 77
AT attachment packet interface
(ATAPI)................................................ 1371
ATAPI timing ....................................... 1924
B
Bit manipulation instructions .................... 88
Bit synchronous circuit ........................... 881
Boundary scan....................................... 1704
Branch instructions ................................... 82
Break detection and processing............... 798
Break on data access cycle...................... 238
Break on instruction fetch cycle.............. 237
Bulk transfers........................................ 1360
Bus state controller (BSC) ...................... 265
Bus timing............................................. 1884
C
Cache ...................................................... 245
Cache structure........................................ 245
Calculating exception handling vector
table addresses ........................................ 142
CAN bus interface................................. 1030
CAN interface ......................................... 933
Canceling software standby mode
(WDT)..................................................... 695
Cascaded operation ................................. 545
Caution on period setting ........................ 626
Changing the division ratio ..................... 132
Changing the multiplication rate............. 130
Changing the PLL multiplication ratio ... 695
Clock frequency control circuit............... 117
Clock operating modes ........................... 120
Clock pulse generator (CPG) .................. 115
Clock timing ......................................... 1878
Clocked synchronous serial format......... 871
CMCNT count timing ............................. 679
Coherency of cache and
external memory ..................................... 260
Command access mode......................... 1175
Communications protocol ..................... 1040
Rev. 1.00 Mar. 14, 2008 Page 1973 of 1984
REJ09B0351-0100