SH7265 Datasheet, PDF (427/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.4 Counter Increment/Decrement for DMA Source/Destination Address Registers
Transfer Data Size 000
Select Bits (SZSEL) (Fixed)
000 (8 bits)
±0
001 (16 bits)
±0
010 (32 bits)
±0
Addressing Mode
SAMOD or DAMOD
001
(Incremen-
tation)
010
(Decremen-
tation)
011
(Rotation)
+1
-1
+1
+2
-2
+2
+4
-4
+4
100
(Two
dimensions)
+1
+2
+4
Table 11.5 shows the relationship between DMA request sources and the DMA-active signal
output control bit for the source. If the DREQ0 to DREQ3 pins are selected as the DMA request
source, select "0: Stop" or "1: Output" as required. The signal corresponding to this setting is
output to the DACT0 to DACT3 external pins (see section 11.9, DMA Acknowledge Signal
Output and DMA-Active Signal Output). If the software trigger is selected, setting of this bit has
no effect, so either 0 or 1 can be set. If other DMA request sources are selected, be sure to set "1:
Output".
Table 11.5 Relationship between DMA Request Sources and DMA-active signal Output
Control Bit for Source
DMA Request Source
0: Stop
Software trigger

DREQ0 pin
Ο
DREQ1 pin
Ο
DREQ2 pin
Ο
DREQ3 pin
Ο
Other DMA request sources ×
[Legend]
Ο: Can be set
×: Setting prohibited
: Setting ignored
SACT Bit Setting
1: Output

Ο
Ο
Ο
Ο
Ο
DCTG Bit Setting
000000
000001
000010
000011
000100
Other than the above
Rev. 1.00 Mar. 14, 2008 Page 391 of 1984
REJ09B0351-0100