SH7265 Datasheet, PDF (664/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the
compare match signal is also generated.
Figure 12.101 shows the timing in this case.
Pφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 12.101 Contention between TGR Write and Compare Match
Rev. 1.00 Mar. 14, 2008 Page 628 of 1984
REJ09B0351-0100