SH7265 Datasheet, PDF (45/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Items
IEBus^TM controller
(IEB)
A/D converter (ADC)
D/A converter (DAC)
AND/NAND flash
memory controller
(FLCTL)
Specification
• IEBus protocol control (layer 2) supported
 Half-duplex asynchronous communications
 Multi-master system
 Broadcast communications function
 Selectable mode (three types) with different transfer speeds
• Includes buffers (dual port RAM) for data transmission and reception
that enable up to 128 bytes of consecutive transmit/reception
(maximum number of transfer bytes in mode 2)
• Operating frequency
 12 MHz, 12.58 MHz
(IEB uses 1/2 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
 18 MHz, 18.87 MHz
(IEB uses 1/3 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
 24 MHz, 25.16 MHz
(IEB uses 1/4 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
 30 MHz, 31.45 MHz
(IEB uses 1/5 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
 36 MHz, 37.74 MHz
(IEB uses 1/6 divided clocks of AUDIO_X1 or AUDIO_X2.)
• 10-bit resolution
• Eight input channels
• A/D conversion initiated by the external trigger or timer trigger
• 8-bit resolution
• Two output channels
• Interface for direct connection with AND-/NAND-type flash memory
• Read/write in sectors
• Two types of transfer modes: Command access mode and sector
access mode (512-byte data + 16-byte management code: with ECC)
• Interrupt request and DMAC transfer request
• Supports 5-byte address (up to 2 Gbits) of flash memory
Rev. 1.00 Mar. 14, 2008 Page 9 of 1984
REJ09B0351-0100