SH7265 Datasheet, PDF (429/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.7 shows the relationship between DMA request sources and the DMA end signal output
control bit. If the DREQ0 to DREQ3 pins are selected as the DMA request source, select 00, 01,
10, or 11 as required. The signal corresponding to this setting is output to the TEND0 to TENDT3
external pins (see section 11.5.3, DMA End Signal Output). If USB_0, USB_1, or a 2DG-related
source is selected, be sure to select 11. If the software trigger or other DMA request source is
selected, setting of this bit has no effect, so either 0 or 1 can be set.
Table 11.7 Relationship between DMA Request Sources and DMA End Signal Output
Control Bit
DMA Request
Source
00: Output
Stop
Software trigger

DREQ0 pin
Ο
DREQ1 pin
Ο
DREQ2 pin
Ο
DREQ3 pin
Ο
USB_0
×
USB_1
×
2DG output
×
2DG BLT input A ×
2DG BLT input B ×
2DG BLT output C ×
Other DMA request 
sources
[Legend]
Ο: Can be set
×: Setting prohibited
: Setting ignored
DTCM Bit Setting
01: Last
10: Last
Read Cycle Write Cycle


Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
×
×
×
×
×
×
×
×
×
×
×
×


11: After DMA DCTG Bit
has Ended Setting

000000
Ο
000010
Ο
000010
Ο
000011
Ο
000100
Ο
000101
Ο
000110
Ο
101111
Ο
110000
Ο
110001
Ο
110010

Other than the
above
Rev. 1.00 Mar. 14, 2008 Page 393 of 1984
REJ09B0351-0100