SH7265 Datasheet, PDF (450/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.17 DMA Two-Dimensional Addressing Row Setting Register (DM2DROWm)
DM2DROWm is a register used to set the number of rows in one block in two-dimensional
addressing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DRN[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 DRN
[15:0]
Undefined R/W DMA Block Row Count
These bits are used to set the number of rows in one block.
00000000_00000000: 1 row
:
11111111_11111111: 65536 rows
Rev. 1.00 Mar. 14, 2008 Page 414 of 1984
REJ09B0351-0100