SH7265 Datasheet, PDF (1515/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
• αRGB555 (F599(H)) converted into a standard format
α:1(H) → F(H) R:1D(H) → 1D(H) G:0C(H) → 0C(H) B:19(H) → 19(H)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α
value
R value
G value
B value
1111010110011001
α value (1 bit)
↓ (copied into 4 bits)
α value (4 bits)
R value (5 bits)
↓ (Unchanged)
R value (5 bits)
G value (5 bits)
↓ (Unchanged)
G value (5 bits)
B value (5 bits)
↓ (Unchanged)
B value (5 bits)
Bit 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α value
R value
G value
B value
1111111010110011001
Figure 28.18 Pixel Format Conversion 2 in Blitter
• α (4 bits) (B(H)) converted into a standard format
α:B(H) → B(H) R:Csasg_r G:Csasg_g B:Csasg_b
The native value is assigned to the α value. To the RGB value, the BRDC_R, BRDC_G, and
BRDC_B bits of the GR_BRDCOL register are assigned.
(2) Summary of Operations between the Blitter and External Memory
The following is a summary of operations between the blitter and external memory:
1. The blitter negates the DMA request signal and accepts a DMA transfer from the external
memory.
2. The SA/SB buffers ((SA1, SA2), (SB1, SB2)), alternately buffer the data received through the
DMA transfer.
3. When the INT_SHFUL and INT_ASHFUL are asserted (if there is source buffer half
agreement), blitter operations are started.
4. Upon completion of blitter operations, a DMA transfer from the DC buffer is performed.
5. The above steps 1 to 4 are repeated until all data processing is completed.
As described above, processing such as image synthesis is possible by reading the external
memory area first, performing blitter processing on the area that has been read next, and writing
back to the same memory area last.
Rev. 1.00 Mar. 14, 2008 Page 1479 of 1984
REJ09B0351-0100