SH7265 Datasheet, PDF (1682/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Table 33.1 States of Power-Down Modes
State*¹
Power-
Down
Mode
Dual-
processor
Transition Conditions

CPG
CPU0
High-Speed
On-Chip
CPU0 RAM0 Cache
CPU1
Register Memory 0 CPU1 Register
High-Speed
On-Chip
RAM0 Cache
Memory 1
On-Chip
RAM
(for Data
Retention)
On-Chip
Peripheral
Modules
RTC
Power External
Supply Memory Means of Exit
Runs Runs Held Runs
Runs Held Runs
Runs
Selective*² Selective*²*³ Runs Auto-

refreshing
Single-
CPU1 executes
Runs Runs Held
processor 0 SLEEP instruction
in dual-processor mode
Runs
Single-
CPU0 executes
processor 1 SLEEP instruction
with STBY bit
in STBCR1 cleared to 0
in dual-processor mode
Runs Halts
Held
Runs
Halts Held Runs
Runs Held Runs
Runs
Runs
Selective*² Selective*²*³ Runs
Selected*² Selective*²*³ Runs
Auto-
• Interrupt
refreshing • Manual reset
• Power-on reset
• CPU address error
Auto-
• Interrupt
refreshing • Manual reset
• Power-on reset
• CPU address error
Dual-sleep
Software
standby
• CPU0 executes
SLEEP instruction
with STBY bit in
STBCR1 cleared to 0
in single-processor 0
mode
• CPU1 executes
SLEEP instruction
in single-processor 1
mode
CPU0 executes
SLEEP instruction
with STBY bit
in STBCR1 set to 1
and DEEP bit to 0
in single-processor 0
mode
Runs Halts
Halts Halts
Held
Held
Deep
standby
CPU0 executes
SLEEP instruction
with STBY bit
in STBCR1 set to 1
and DEEP bit to 1
in single-processor 0
mode
Halts Halts Halts
Runs
Halts
(contents
are held)
Halts
(contents
are not
held)
Halts Held Runs
Halts Held
Halts
(contents
are held)
Halts Halts
Halts
(contents
are not
held)
Runs
Selective*² Selective*²*³ Runs
Auto-
• Interrupt
refreshing • Manual reset
• Power-on reset
• CPU address error
Halts
(contents
are held)
Halts
Runs*³
Runs
Should be • NMI interrupt
put into • IRQ interrupt
self-
• Manual reset
refreshing • Power-on reset
mode
Halts
Halts
(contents
are held*⁴)
Runs*³
Halts
Should be • NMI interrupt*⁵
put into • IRQ interrupt*⁵
self-
• Manual reset*⁵
refreshing • Power-on reset*⁵
mode
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
2. By specifying the module standby function, individual on-chip peripheral modules
(including the RTC) can be halted. To specify the module standby function, set the
corresponding MSTP bit in STBCR2 to STBCR7 to 1. To cancel the module standby
function, clear the MSTP bit to 0. For the H-UDI and UBC, the module standby function
can also be canceled by power-on reset.
3. RTC operates when the START bit in the RCR2 register is set to 1. For details, see
section 15, Realtime Clock (RTC).
4. Setting the bits RRAMKP3 to RRAMKP0 in the RRAMKP register to 1 enables to retain
the data in the corresponding area on the on-chip RAM (for data retention) during the
transition to deep standby mode.
5. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual
reset or power-on reset). However, when deep standby mode is canceled by the NMI
interrupt or IRQ interrupt, power-on reset exception handling is executed instead of
interrupt exception handling. The power-on reset exception handling is executed also in
the cancellation of deep standby mode by manual reset.
Rev. 1.00 Mar. 14, 2008 Page 1646 of 1984
REJ09B0351-0100