SH7265 Datasheet, PDF (1587/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.3.3 DMA Control Register (DMACR)
DMACR is a 32-bit readable/writable register that sets DMA transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
TRAN TRAN
DOCTL ICTL
-
-
-
-
-
-
DMA DMA
OMD IMD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R
R R/W R/W
Bit
Bit Name
31 to 10 
Initial
Value
All 0
9
TRANDOCTL 0
8
TRANICTL 0
7 to 2 
All 0
1
DMAOMD 0
0
DMAIMD
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMACR Setting Predetermined 2
This bit should be set to 1.
R/W DMACR Setting Predetermined 1
This bit should be set to 1.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Output DMA Transfer Mode
Enables data output from the DOUT_RAM with DMA
transfer. When this bit is set to 1, the TRANOCTL bit
in this register should be set to 1.
0: Disables DMA transfer.
1: Enables DMA transfer.
R/W Input DMA Transfer Mode
Enables data input to the DIN_RAM with DMA
transfer. When this bit is set to 1, the TRANICTL bit in
this register should be set to 1.
0: Disables DMA transfer.
1: Enables DMA transfer.
Rev. 1.00 Mar. 14, 2008 Page 1551 of 1984
REJ09B0351-0100