SH7265 Datasheet, PDF (18/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

12.7.1 Module Standby Mode Setting ......................................................................... 625
12.7.2 Input Clock Restrictions ................................................................................... 625
12.7.3 Caution on Period Setting ................................................................................. 626
12.7.4 Contention between TCNT Write and Clear Operations.................................. 626
12.7.5 Contention between TCNT Write and Increment Operations........................... 627
12.7.6 Contention between TGR Write and Compare Match ...................................... 628
12.7.7 Contention between Buffer Register Write and Compare Match ..................... 629
12.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 630
12.7.9 Contention between TGR Read and Input Capture........................................... 631
12.7.10 Contention between TGR Write and Input Capture.......................................... 632
12.7.11 Contention between Buffer Register Write and Input Capture ......................... 633
12.7.12 TCNT2 Write and Overflow/Underflow Contention in
Cascade Connection.......................................................................................... 633
12.7.13 Counter Value during Complementary PWM Mode Stop ................................ 635
12.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 635
12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 636
12.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 637
12.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 638
12.7.18 Contention between TCNT Write and Overflow/Underflow............................ 639
12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronized PWM Mode...................................................................... 639
12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized
PWM Mode....................................................................................................... 640
12.7.21 Interrupts in Module Standby Mode ................................................................. 640
12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 640
12.8 MTU2 Output Pin Initialization........................................................................................ 641
12.8.1 Operating Modes .............................................................................................. 641
12.8.2 Reset Start Operation ........................................................................................ 641
12.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 642
12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc. .............................................................................. 643
Section 13 Compare Match Timer (CMT) ........................................................ 673
13.1 Features............................................................................................................................. 673
13.2 Register Descriptions........................................................................................................ 674
13.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 675
13.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 676
13.2.3 Compare Match Counter (CMCNT) ................................................................. 678
13.2.4 Compare Match Constant Register (CMCOR) ................................................. 678
13.3 Operation .......................................................................................................................... 679
Rev. 1.00 Mar. 14, 2008 Page xviii of xxxvi