SH7265 Datasheet, PDF (1424/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 AT Attachment Packet Interface (ATAPI)
(8) DMA transfer count register (ATAPI_DMA_TRANS_CNT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
DTRC[28:16]
Initial value: ^-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTRC[15:1]
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name Value
R/W Description
31 to 29 

R
Reserved
28 to 1 DTRC[28:1] H'0000000 R/W These bits specify a DMA transfer count.
Bits 28 to 0 are used to set a DMA transfer count on
a byte basis.
Bit 0 is ignored because the ATAPI data bus operates
in16-bit (1-word) units.
0


R
Reserved
Note: This count value will not change even after DMA becomes active; it will retain its setting.
Rev. 1.00 Mar. 14, 2008 Page 1388 of 1984
REJ09B0351-0100