SH7265 Datasheet, PDF (1600/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 AESOP
29.4 Operations
For AAC encoding processing, pipeline processing of two steps (the first-half and second-half) is
performed. Input the data to DIN_RAM and output the data from DOUT_RAM by DMA transfer.
29.4.1 DMA Transfer Operation
Figure 29.3 shows timings of the AAC encoding processing.
The following describes the stream of a tune that consists of N frames.
Registers should be set so that the desired operating conditions should be satisfied in initial
settings. A DMA request is automatically generated and PCM data is written to the DIN_RAM
with the DMA transfer. 2048 samples of PCM data are transferred at the start of the tune, then the
first half of AESOP processing is executed. When the DIN_RAM is released during the AESOP
processing, a DMA request is generated and the next 1024 samples of PCM data are written to the
DIN_RAM. Subsequently, 1024 samples of PCM data are transferred and the first half and second
half of the AESOP processing are executed in parallel. This operation is repeated for the number
of frames to be transferred.
When the second half of the AESOP processing is complete, a DMA request is generated and
stored AAC-formatted data is read from the DOUT_RAM. Since AAC output data is transferred
in 4-Kbyte units, a DMA request is generated when 4 Kbytes of data are in the DOUT_RAM after
the second half of the AESOP processing ends. Data stored in the DOUT_RAM is byte aligned in
each frame and stored continuously.
When data of the tune has been transferred, one frame of 0 data should be transferred. Thus,
processing of the N-th frame data is executed.
If the DOUT_RAM holds data less than 4 Kbytes when the second half of AESOP processing for
the final PCM input data is complete, the data should be forcibly transferred by register setting.
Rev. 1.00 Mar. 14, 2008 Page 1564 of 1984
REJ09B0351-0100