SH7265 Datasheet, PDF (2011/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Format of single-precision
foating-point number ............................... 94
FPU exception sources ........................... 104
FPU-related CPU instructions .................. 87
Full-scale error...................................... 1124
G
General illegal instructions ..................... 154
General registers ....................................... 47
Global base register (GBR) ...................... 49
H
Halt mode ............................................. 1006
H-UDI interrupt ............................ 197, 1703
H-UDI related pin timing...................... 1956
H-UDI reset .......................................... 1703
I
I/O port timing ...................................... 1955
I/O ports................................................ 1611
I²C bus format......................................... 862
I²C bus interface 3 (IIC3) ....................... 843
ID reorder ............................................... 954
IEBus bit format ................................... 1051
IEBus communications protocol........... 1036
IEBus controller (IEB) ...................... 1035
IIC3 timing ........................................... 1907
Immediate data ......................................... 56
Immediate data accessing ......................... 56
Immediate data format.............................. 53
Influences on absolute precision........... 1128
Initial values of control registers .............. 51
Initial values of general registers .............. 51
Initial values of system registers............... 51
Instruction features ................................... 54
Instruction format ..................................... 63
Instruction set ........................................... 67
Integer division instructions.................... 155
Internal arbitration for transmission...... 1010
Interrupt controller (INTC) ..................... 161
Interrupt exception handling ................... 152
Interrupt exception vectors and
priorities .................................................. 202
Interrupt priority level............................. 151
Interrupt response time ........................... 211
Interrupt transfers.................................. 1360
IRQ interrupts ......................................... 198
Isochronous transfers ............................ 1362
J
Jump table base register (TBR)................. 49
L
List of DMA transfer conditions ............. 428
Load-store architecture ............................. 54
Local acceptance filter mask (LAFM) .... 945
Logic operation instructions...................... 80
M
Mailbox........................................... 932, 936
Mailbox configuration ............................ 944
Mailbox control....................................... 932
Manual reset............................................ 146
Master receive operation......................... 865
Master transmit operation ....................... 863
Memory-allocated cache ......................... 260
Message control field.............................. 941
Message data fields ................................. 946
Message receive sequence .................... 1024
Message transmission request..... 1010, 1019
Micro processor interface (MPI)............. 932
Module standby mode setting ................. 841
MTU2 functions...................................... 458
MTU2 interrupts ..................................... 610
Rev. 1.00 Mar. 14, 2008 Page 1975 of 1984
REJ09B0351-0100