SH7265 Datasheet, PDF (1456/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.3.6 Interrupt Reset Control Register for Graphics (GR_INTDIS)
The register GR_INTDIS cancels 2DG interrupts. Interrupt signals are deasserted by writing 1 to
the corresponding bits in this register. Furthermore, the IRQ_DEMPT, IRQ_ASHFUL,
IRQ_DHFUL, IRQ_SHFUL, INT_VSYC, INT_UDFL, INT_ FILD, and INT_GR bits in
GR_IRSTAT are cleared by writing 1 to the corresponding bits in this register. Note, however,
that the INT_DEMP, INT_ASHFUL, INT_DHFUL, and INT_SHFUL bits in GR_IRSTAT are
not cleared even if 1 is written to the corresponding bits in this register (the hardware
automatically handles clearing of these bits). When a 1 is written to any of these bits, the hardware
automatically sets the bit to its initial value. For details on interrupts, see section 28.4.5, Interrupts.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
DIS_ DIS_ DIS_
VSYC UDFL FILD
-
-
-
DIS_
DEMPT
-
DIS_ DIS_ DIS_
ASHFUL DHFUL SHFUL
-
-
-
DIS_
GR
Initial value: -
0
0
0
-
-
-
0
-
0
0
0
-
-
-
0
R/W: R
WWW
R
R
R
W
R
W
WW
R
R
R
W
Bit
Bit name
31 to 15 
14
DIS_VSYC
Initial
Value
R/W
Undefined R
0
W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Output Block VSYNC Input Interrupt Cancellation
This bit cancels a VSYNC input interrupt for the
output block.
0: Retains the current status.
1: Cancels a VSYNC input interrupt for the output
block.
Rev. 1.00 Mar. 14, 2008 Page 1420 of 1984
REJ09B0351-0100