SH7265 Datasheet, PDF (1503/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

VICLK
(27 MHz)
VIHSYNC
VICLKENB
VIVSYNC
Section 28 2D Graphics Engine (2DG)
Each signal input from the video decoder is synchronous with the rising edge of VICLK (for both NTSC/PAL).
Figure 28.7 Relations between Externally Input Sync Signal and VICLK
DCLKIN
HSYNC_dck
(Internal)
The WPH bits
in the
MGR_MIXHTMG
register
The ALLPH bits in the
MGR_MIXHS register
HVLD_dck
(Internal)
VSYNC_dck
(Internal)
The PDPH bits in the
MGR_MIXHTMG register
The VLDPH bits in the
MGR_MIXHS register
Each internally generated sync signal is synchronous with the rising edge of DCLKIN (for both NTSC/PAL).
Figure 28.8 Relations between Internal Generated Sync Signals and DCLKIN
Rev. 1.00 Mar. 14, 2008 Page 1467 of 1984
REJ09B0351-0100