SH7265 Datasheet, PDF (1953/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 36 Electrical Characteristics
Table 36.20 NAND Type Flash Memory Interface Timing
Conditions: VCC = PLLVCC = 1.1 to 1.3 V, USBDVCC = 1.1 to 1.3 V, USBAVCC = 1.1 to 1.3 V,
PVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAPVCC = 3.0 to 3.6 V,
2DGAPVCC0 = 3.0 to 3.6 V, 2DGAPVCC1 = 3.0 to 3.6 V,
VSS = PLLVSS = USBAVSS = AVSS = USBAPVSS = 2DGAPVSS0 = 2DGAPVSS1 = 0 V,
Ta = −40 to 85 °C
Item
Command output setup time
Command output hold time
Data output setup time
Data output hold time
Command to address transition
time 1
Command to address transition
time 2
FWE cycle time
FWE low pulse width
Symbol Min.
Max.
tNCDS
2 × tfcyc − 10 
tNCDH
1.5 × tfcyc − 5 
tNDOS
0.5 × twfcyc − 5 
tNDOH
0.5 × twfcyc − 10 
tNCDAD1
1.5 × tfcyc − 10 
Unit
ns
ns
ns
ns
ns
tNCDAD2
2 × tfcyc − 10

ns
tNWC
twfcyc − 5

ns
tNWP
0.5 × twfcyc − 5 
ns
FWE high pulse width
tNWH
0.5 × twfcyc − 5 
ns
Address to ready/busy transition time tNADRB
Command to ready/busy transition
time
tNCDRB
Ready/busy to data read transition
time 1
tNRBDR1
Ready/busy to data read transition
time 2
tNRBDR2
FSC cycle time
tNSCC
FSC low pulse width
tNSP

32 × tpcyc ns

10 × tpcyc ns
1.5 × tfcyc

ns
32 × tpcyc

ns
twfcyc − 5

ns
0.5 × twfcyc − 5 
ns
FSC high pulse width
tNSPH
0.5 × twfcyc − 5 
ns
Figure
Figures 36.49,
36.53
Figures 36.49,
36.50, 36.52,
36.53
Figures 36.49,
36.50
Figure 36.50
Figures 36.50,
36.52
Figures 36.49,
36.50, 36.52,
36.53
Figures 36.50,
36.52
Figures 36.50,
36.51
Figure 36.51
Figures 36.51,
36.53
Figure 36.51
Rev. 1.00 Mar. 14, 2008 Page 1917 of 1984
REJ09B0351-0100