SH7265 Datasheet, PDF (1695/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
33.2.8 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access (read/write) from
CPU0 to each page of the high-speed on-chip RAM0.
Setting the RAMEn (n = 0 to 3) bit in SYSCR1 to 1 enables access to page n. Clearing the
RAMEn bit to 0 disables access to page n. In this case, an undefined value is returned when
reading data or fetching an instruction from page n, and writing to page n is ignored. The initial
value of the RAMEn bit is 1.
When clearing the RAMEn bit to 0, be sure to execute instructions to read from and write to the
same arbitrary address in page n before clearing the RAMEn bit. If not executed, the data last
written to page n may not be actually written to the high-speed on-chip RAM.
SYSCR1 should be set by the program that is placed in a space other than the high-speed on-chip
RAM space. Furthermore, an instruction to read SYSCR1 should be located immediately after the
instruction to write to SYSCR1. Otherwise, normal access to the high-speed on-chip RAM is not
guaranteed.
Note: When writing to this register, see section 33.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
- RAME3 RAME2 RAME1 RAME0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R/W R/W R/W R/W
Bit
7 to 4
Initial
Bit Name Value

All 1
3
RAME3 1
2
RAME2 1
R/W Description
R
Reserved
These bits are always read as 1. The write value should
always be 1.
R/W RAM Enable 3 (page 3 of high-speed on-chip RAM0*)
0: Access to page 3 is disabled.
1: Access to page 3 is enabled.
R/W RAM Enable 2 (page 2 of high-speed on-chip RAM0*)
0: Access to page 2 is disabled.
1: Access to page 2 is enabled.
Rev. 1.00 Mar. 14, 2008 Page 1659 of 1984
REJ09B0351-0100