SH7265 Datasheet, PDF (957/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.4.4 Transmit Operation
Transmission can be controlled either by DMA or interrupt.
DMA control is preferred to reduce the processor load. In DMA control mode the processor will
only receive interrupts if there is an underflow or overflow of data or the DMAC has finished its
transfer.
The alternative method is using the interrupts that the SSIF module generates to supply data as
required.
When disabling the SSIF module, the clock* must be kept supplied to the SSIF until the IIRQ bit
indicates that the module is in the idle state.
Figure 19.20 shows the transmit operation in DMA control mode, and figure 19.21 shows the
transmit operation in interrupt control mode.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.
Rev. 1.00 Mar. 14, 2008 Page 921 of 1984
REJ09B0351-0100