SH7265 Datasheet, PDF (372/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
(b) Procedure for Transition to and Recovery from Self-Refresh Mode
Figure 10.26 shows the procedure for transitioning to and recovering from self-refresh mode.
Access enabled state:
Operation enabled (EXENB in SDCmCNT = 1)
Auto-refresh enabled (DRFEN in SDRFCNT1 = 1)
Initialization sequence:
(1) Halt any DMA access to SDRAM area
Keep CPU from accessing SDRAM area
(2) Disable access to all SDRAMC channels (EXENB = 0) by
a program placed in other than SDRAM area
(3) Make sure that EXENB has been cleared to 0
Start self-refreshing:
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Set DSFEN bit to 1 by a program placed in other than SDRAM area
Self-refresh mode
End self-refreshing:
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Clear DSFEN bit to 0 by a program placed in other than SDRAM area
Enable access:
Enable access to SDRAMC (EXENB = 1) by
a program placed in other than SDRAM area
Access enabled state:
(DRFEN = 1, EXENB = 1)
Figure 10.26 Procedure for Transition to and Recovery from Self-Refresh Mode
Notes: Before transitioning to or recovering from self-refresh mode it is necessary to halt
SDRAM access to the affected channel. Consequently, it is not possible to transition to or
recover from self-refresh mode while programs or DMA operations that access SDRAM
are in progress. Pay attention to the following points when writing programs.
Rev. 1.00 Mar. 14, 2008 Page 336 of 1984
REJ09B0351-0100