SH7265 Datasheet, PDF (1459/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.3.7 DMAC-Request Control Register for Graphics (GR_DMAC)
The register GR_DMAC sets DMA transfer and CPU transfer control methods for SA, SB, DC
and SE buffers. Note that the settings for this register should be the same as the corresponding
settings in the DMAC.
Bit: 31
-
Initial value: -
R/W: R
Bit: 15
-
Initial value: -
R/W: R
30 29 28 27 26 25 24 23
- SZSEL2 SZSEL1 -
-
-
-
-
-
1
1
-
-
-
-
-
R R/W R/W R
R
R
R
R
14 13 12 11 10 9
8
7
-
DM1_DSEL DM2_DSEL DM34_DSEL
-
-
0
0
0
0
0
0
-
R R/W R/W R/W R/W R/W R/W R
22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
6
5
4
3
2
1
0
-
DM1_MSEL DM2_MSEL DM34_MSEL
-
0
1
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit
Bit name
31, 30 
29
SZSEL2
28
SZSEL1
27 to 14 
Initial
Value
R/W
Undefined R
1
R/W
1
R/W
Undefined R
Description
Reserved
The read value is undefined. The write value should
always be 0.
Output Block DMA Transfer Data Size
This bit sets the size (number of bits) of data used for
DMA transfer in the output block.
0: 16 bits
1: 32 bits
Blitter DMA Transfer Data Size
This bit sets the size (number of bits) of data used for
DMA transfer in the blitter.
0: 16 bits
1: 32 bits
Reserved
The read value is undefined. The write value should
always be 0.
Rev. 1.00 Mar. 14, 2008 Page 1423 of 1984
REJ09B0351-0100