SH7265 Datasheet, PDF (29/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

27.4.1 Data Transfer Modes....................................................................................... 1391
27.4.2 Initialization Procedure................................................................................... 1392
27.4.3 PIO Transfer Mode Operation Procedure ....................................................... 1392
27.4.4 Multiword DMA Transfer Mode Operation Procedure .................................. 1393
27.4.5 Ultra DMA Transfer Mode Operation Procedure ........................................... 1395
27.4.6 ATAPI Device Hardware Reset Procedure..................................................... 1397
27.5 DIRECTION Pin............................................................................................................. 1398
27.6 Usage Note...................................................................................................................... 1398
Section 28 2D Graphics Engine (2DG) ...........................................................1399
28.1 Features........................................................................................................................... 1399
28.2 Input/Output Pins............................................................................................................ 1401
28.3 Register Descriptions...................................................................................................... 1402
28.3.1 Blit Function Setting Register for Graphics (GR_BLTPLY).......................... 1405
28.3.2 Mixing Function Setting Register for Graphics (GR_MIXPLY).................... 1407
28.3.3 Operation Status Register for Graphics (GR_DOSTAT)................................ 1408
28.3.4 Interrupt Status Register for Graphics (GR_IRSTAT) ................................... 1412
28.3.5 Interrupt Mask Control Register for Graphics (GR_INTMSK)...................... 1417
28.3.6 Interrupt Reset Control Register for Graphics (GR_INTDIS) ........................ 1420
28.3.7 DMAC-Request Control Register for Graphics (GR_DMAC)....................... 1423
28.3.8 Source A&B Read-In-Area Setting Register for Blitter (GR_SABSET)........ 1426
28.3.9 Destination C Write Area Setting Register for Blitter (GR_DCSET)............. 1428
28.3.10 Source E Read-In Area Setting Register for Output Block
(MGR_SESET) ............................................................................................... 1429
28.3.11 Pixel Format Setting Register for Graphics (GR_PIXLFMT) ........................ 1431
28.3.12 Operation Mode Setting Register for Blitter (GR_BLTMODE)..................... 1433
28.3.13 Resize Display Setting Register for Graphics (GR_RISZSET) ...................... 1435
28.3.14 Resize Mode Select Register for Blitter (GR_RISZMOD)............................. 1437
28.3.15 Resize Delta Setting Register for Blitter (GR_DELT).................................... 1438
28.3.16 Resize Horizontal Starting Phase Register for Blitter (GR_HSPHAS)........... 1440
28.3.17 Resize Vertical Starting Phase Register for Blitter (GR_VSPHAS)............... 1441
28.3.18 Resize Horizontal Delta Setting Register for Output Block
(MGR_HDELT).............................................................................................. 1442
28.3.19 Resize Horizontal Starting Phase Register for Output Block
(MGR_HPHAS).............................................................................................. 1443
28.3.20 Logical Operation Input Data Register for Blitter (GR_LGDAT) .................. 1444
28.3.21 Chromakey Target Color Data Register for Blitter (GR_DETCOL) .............. 1445
28.3.22 Replacement Color Data Register for Blitter Blending (GR_BRDCOL) ....... 1446
28.3.23 Blend 1 Control Register for Blitter (GR_BRD1CNT) .................................. 1447
28.3.24 Mixing Mode Setting Register for Output Block (MGR_MIXMODE).......... 1450
Rev. 1.00 Mar. 14, 2008 Page xxix of xxxvi