SH7265 Datasheet, PDF (1693/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
2
MSTP62 1
R/W Module Stop 62
When set to 1, the clock supply to the SSIF5 is halted.
0: SSIF5 runs.
1: Clock supply to SSIF5 is halted.
1, 0 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
33.2.7 Standby Control Register 7 (STBCR7)
STBCR7 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes.
Note: When writing to this register, see section 33.4, Usage Notes.
Bit: 7
MSTP
77
Initial value: 1
R/W: R/W
6
MSTP
76
1
R/W
5
MSTP
75
1
R/W
4
MSTP
74
1
R/W
3
MSTP
73
1
R/W
2
MSTP
72
1
R/W
1
MSTP
71
1
R/W
0
MSTP
70
1
R/W
Initial
Bit Bit Name Value R/W Description
7
MSTP77 1
R/W Module Stop 77
When set to 1, the clock supply to the CMT0/CMT1 is halted.
0: CMT0/CMT1 run.
1: Clock supply to CMT0/CMT1 is halted.
6
MSTP76 1
R/W Module Stop 76
When set to 1, the clock supply to the CMT2/CMT3 is halted.
0: CMT2/CMT3 run.
1: Clock supply to CMT2/CMT3 is halted.
5
MSTP75 1
R/W Module Stop 75
When set to 1, the clock supply to the AESOP is halted.
0: AESOP runs.
1: Clock supply to AESOP is halted.
Rev. 1.00 Mar. 14, 2008 Page 1657 of 1984
REJ09B0351-0100