SH7265 Datasheet, PDF (1787/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Module
Name Register Name
Abbreviation
2DG
Mixing mode setting register for
output block (synchronized with
VSYNC)
MGR_MIXMODE
Panel-output horizontal timing
setting register for output block
(synchronized with VSYNC)
MGR_MIXHTMG
Panel-output mixing horizontal
valid area setting register for
output block (synchronized with
VSYNC)
MGR_MIXHS
Panel-output vertical timing setting MGR_MIXVTMG
register for output block
(synchronized with VSYNC)
Panel-output mixing vertical valid MGR_MIXVS
area setting register for output
block (synchronized with VSYNC)
Output SYNC setting register for GR_VSDLY
graphics
Video DAC timing setting register VDAC_TMC
AESOP Software reset register
SWRSR
Encoding processing initialization RPRSR
register
DMA control register
DMACR
DMA transfer register for
DIN_RAM buffer write
DMADI
DMA transfer register for
DOUT_RAM buffer read
DMADO
Event mask register
EVMSR
Event clear register
EVCLR
Setting-predetermined register 1 MBOTR
Setting-predetermined register 2 BACCR
Setting-predetermined register 3 ACESR
Audio processing information
setting register
ADIFR
Setting-predetermined register 4 TBRSR
Header setting register
HEADR
Section 35 List of Registers
Number
of Bits Address
32
H'E8000098
Access
Size
16, 32
32
H'E80000A0 16, 32
32
H'E80000A4 16, 32
32
H'E80000A8 16, 32
32
H'E80000AC 16, 32
32
H'E80000C4 16, 32
32
H'EA000000 32
32
H'FFA10000 32
32
H'FFA10004 32
32
H'FFA10008 32
32
H'FFA1000C 32
32
H'FFA10010 32
32
H'FFA1001C 32
32
H'FFA10024 32
32
H'FFA10028 32
32
H'FFA1002C 32
32
H'FFA10030 32
32
H'FFA10034 32
32
H'FFA10038 32
32
H'FFA1003C 32
Rev. 1.00 Mar. 14, 2008 Page 1751 of 1984
REJ09B0351-0100