SH7265 Datasheet, PDF (1180/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W
22
4ECCCO 0
R/W
RRECT
21 to 19 —
All 0 R
18
SNAND 0
R/W
17
QTSEL 0
R/W
16
—
0
R
Description
4-Symbol ECC Circuit Correction Execution
Specifies to execute error correction for a single sector
when the 4-symbol ECC circuit is used. The FLCTL
suspends sector reading on detection of an ECC error
and starts error pattern generation by the 4-symbol
ECC circuit.
0: Error pattern is not output but only ECC is output.
1: Reading of sectors is suspended on detection of an
ECC error.
Reserved
These bits are always read as 0. The write value should
always be 0.
Large-Capacity NAND Flash Memory Select
This bit is used to specify 1-Gbit or larger NAND flash
memory with the page configuration of 2048 + 64 bytes,
and 1-Gbit or larger AG-AND flash memory.
0: When flash memory with the page configuration of
512 + 16 bytes, or AND flash memory is used.
1: When NAND flash memory with the page
configuration of 2048 + 64 bytes, or 1-Gbit or larger
AG-AND flash memory is used.
Note: When TYPESEL = 0, this bit should not be
set to 1.
Select Dividing Rates for Flash Clock
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with FCKSEL.
• QTSEL = 0, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by two and uses it as FCLK.
• QTSEL = 0, FCKSEL = 1: Uses a clock (Pφ)
provided from the CPG as FCLK.
• QTSEL = 1, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by four and uses it as FCLK.
• QTSEL = 1, FCKSEL = 1: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 14, 2008 Page 1144 of 1984
REJ09B0351-0100