SH7265 Datasheet, PDF (422/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit
Name
27 to 24 OPSEL
[3:0]
Initial
Value
R/W Description
Undefined R/W Single Operand Transfer Data Count Select
These bits are used to set the number of data units to be
transferred in single operand transfer. The amount of data
set by theses bits is transferred continuously. Channel
arbitration is not performed until this amount of data has
been transferred (single operand transfer).
These bits are invalid when non-stop transfer (DSEL = 11) is
selected in the DMA transfer condition select bits (DSEL) of
DMA control register A (DMCNTAn).
0000: 1 data unit
0001: 2 data units
0010: 4 data units
0011: 8 data units
0100: 16 data units
0101: 32 data units
0110: 64 data units
0111: 128 data units
1000 to 1111: Setting prohibited
Note: Set the DMA current byte count register (DMCBCTn)
so that it becomes H000 0000 when the last data is
transferred via operand transfer.
• When the transfer data size is set to 8 bits
(SZSEL = 000)
Integral multiple of the number of data units
transferred in single operand transfer (×1, ×2, ×3,
and so on)
• When the transfer data size is set to 16 bits
(SZSEL = 001)
Number of data units transferred in single operand
transfer multiplied by two (×2, ×4, ×6, and so on)
• When the transfer data size is set to 32 bits
(SZSEL = 010)
Number of data units transferred in single operand
transfer multiplied by four (×4, ×8, ×12, and so on)
Operation is not guaranteed when values other than the
above are set. For details, see section 11.3.3, DMA Current
Byte Count Register (DMCBCTn) and section 11.3.6, DMA
Reload Byte Count Register (DMRBCTn).
Rev. 1.00 Mar. 14, 2008 Page 386 of 1984
REJ09B0351-0100