SH7265 Datasheet, PDF (958/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
(1) Transmission Using DMA Controller
Start
Release from reset,
set SSICR configuration bits.
Set up DMA controller to
provide transmission data as
required.
Enable SSIF module,
enable DMA,
enable error interrupts.
Wait for interrupt from DMAC or SSIF.
Set TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
UIEN = 1, OIEN = 1,
TIE = 1
Yes
SSIF error interrupt?
No
No
DMAC:
End of Tx data?
Yes
Yes
More data to be sent?
No
Disable SSIF module,
disable DMA,
disable error interrupts,
enable idle interrupt.
EN = 0,
UIEN = 0, OIEN = 0,
IIEN = 1, TIE = 0
Wait for idle interrupt
from SSIF module.
End*
Note: * If the SSIF encounters an error interrupt underflow/overflow,
go back to the start in the flowchart again.
Figure 19.20 Transmission Using DMA Controller
Rev. 1.00 Mar. 14, 2008 Page 922 of 1984
REJ09B0351-0100