SH7265 Datasheet, PDF (1737/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 User Debugging Interface (H-UDI)
34.5 Operation
34.5.1 TAP Controller
Figure 34.2 shows the internal states of the TAP controller. This state machine conforms to the
state transitions defined by JTAG.
1 Test -logic-reset
0
1
0 Run-test/idle
1
Select-DR
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 34.2 TAP Controller State Transitions
Note:
The transition condition is the TMS value at the rising edge of TCK. The TDI value is
sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details
on transition timing of the TDO value, see section 34.5.3, TDO Output Timing. The TDO
is at high impedance, except with shift-DR and shift-IR states. During the change to TRST
= 0, there is a transition to test-logic-reset asynchronously with TCK.
Rev. 1.00 Mar. 14, 2008 Page 1701 of 1984
REJ09B0351-0100