SH7265 Datasheet, PDF (232/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
(9) DREQER8
Bit Bit Name
7 to 2 
1
RCAN
RM01
0
RCAN
RM00
Initial
Value R/W
All 0 R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1: DMA transfer request is enabled and CPU interrupt
request is disabled.
Rev. 1.00 Mar. 14, 2008 Page 196 of 1984
REJ09B0351-0100