SH7265 Datasheet, PDF (1494/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
28.3.30 Video DAC Timing Setting Register (VDAC_TMC)
The setting in this register is for the timing of output to a monitor.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
edgesel
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit name Value
R/W Description
31 to 1 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
0
edgesel
0
R/W Output timing setting
This bit controls the timing of output to a monitor.
0: Output of analog RGB data is synchronized with
rising edges of DLCKIN.
1: Output of analog RGB data is synchronized with
falling edges of DLCKIN.
Note: When writing to this register, stop the 2DG module beforehand.
Rev. 1.00 Mar. 14, 2008 Page 1458 of 1984
REJ09B0351-0100