SH7265 Datasheet, PDF (424/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Initial
Bit
Name Value
R/W Description
10 to 8 DAMOD Undefined R/W Destination Address Direction Control
[2:0]
These bits are used to set a destination address counting
direction.
If these bits are set to 100 (two-dimensional addressing),
the source address direction control bits (SAMOD) cannot
be set to 100. Two-dimensional addressing (100) can be set
only in channels 0 to 7. Do not set two-dimensional
addressing in other channels.
000: Fixed
001: Incrementation
010: Decrementation
011: Rotation
100: Two-dimensional addressing
101 to 111: Setting prohibited
7 to 4 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
3
SACT Undefined R/W Source DMA-active signal Output Control
This bit is used to control the output of the DMA-active
signal (DMAACTSk_N) for the source corresponding to the
request source set in the DCTG bits. When this bit is set to
0, output of the DMAACTS_N signal is disabled and the
signal is fixed high. When this bit is set to 1, a low-level
DMAACTS_N is output (showing that DMA is active) from
the next cycle after the start of the DMAC read cycle. When
an on-chip peripheral module is selected as the DMA
request source, be sure to set this bit to 1 (see table 11.5).
0: Disables output of the DMA-active signal for the source
1: Outputs DMA-active signal for the source during read
access
Note: In the context where indication of transfer request
source number, k, is not necessary, the signal name
is expressed as DMAACTS_N with k omitted.
Rev. 1.00 Mar. 14, 2008 Page 388 of 1984
REJ09B0351-0100