SH7265 Datasheet, PDF (363/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC)
CKIO
Multiple reads
SDRAM command
ACT RD RD RD RD PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all-banks command
Figure 10.15 Multiple Read Timing Example
(Multiple Reads of 4 Data Units, Shortest Timing Settings)
Consecutive Read Commands Issued
Multiple writes
CKIO
SDRAM command
ACT WR WR WR WR PRA
Data bus
d0
d1
d2
d3
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
Figure 10.16 Multiple Write Timing Example
(Multiple Writes of 4 Data Units, Shortest Timing Settings)
Consecutive Write Commands Issued
Rev. 1.00 Mar. 14, 2008 Page 327 of 1984
REJ09B0351-0100