SH7265 Datasheet, PDF (1124/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 IEBus^TM Controller (IEB)
21.4 Data Format
21.4.1 Transmission Format
Figure 21.6 shows the relationship between the transfer format and each register during the IEBus
data transmission.
[In master transmission]
Communications frame Master address
Slave address
Control bits
Message length bits
Data bits
Register
IEAR1, IEAR2
IESA1, IESA2
IEMCR
IETBFL
IETB001 to IETB128
[In slave transmission]
Communications frame ^{Master address}
Slave address
Control bits
Message length bits
Data bits
Register
(*2)
(*1)
(*3)
IEAR1, IEAR2
IETBFL
IETB001 to IETB128
Notes:
1. In slave transmission, the received master address is not saved. If the unit is locked,
address comparison performed.
2. The received slave address is compared with IEAR1 and IEAR2, and if these addresses
match, operation continues.
3. In slave transmission, the received control bits are not saved. The received control bits
are decoded to decide the subsequent operation.
Figure 21.6 Relationship between Transfer Format
and Each Register during IEBus Data Transmission
Rev. 1.00 Mar. 14, 2008 Page 1088 of 1984
REJ09B0351-0100