SH7265 Datasheet, PDF (1487/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 28 2D Graphics Engine (2DG)
Initial
Bit
Bit name Value
R/W Description
15 to 13 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
12
MVON
0
R/W External Moving Picture Input Specification
This bit sets to turn on or off the external moving
picture input.
0: Turns off the external moving picture input for the
system (synchronization with VSYNC generated
internally)
1: Turns on the external moving picture input for the
system with external moving picture input (pseudo-
synchronization with external VIVSYNC)
11 to 9 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
8
CBCR
0
R/W CbCr Bit Position Swapping
This bit selects whether CbCr position is swapped or
not when the YCbCr422 →YCbCr444 conversion is
performed.
0: Not swapped
1: Swapped
7 to 1 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
0
VLD_N
0
R/W VICLKENB Polarity Select
This bit selects the polarity of VICLKENB which is the
VALID signal for external moving picture input.
0: L polarity during VALID
1: H polarity during VALID
Notes: 1. For symbols, see figure 28.55.
2. For details on the CBCR bit, see figure 28.15.
3. When a system with the low quality external moving picture input has been selected
and displays only the graphic image, the MVON bit should be cleared to 0. By this
setting, synchronization errors can be prevented by using internal SYNC signal, and
this improves the quality of display. When MVON is set to 1, VIHSYNC or VIVSYNC
which is synchronous with external moving picture input should be input.
4. When αRGB555 is selected for the pixel format (SE_FMT in GR_PIXFMT = 1) and α
data of the pixel data is 1, four bits of α data are replaced with CHG_A.
Rev. 1.00 Mar. 14, 2008 Page 1451 of 1984
REJ09B0351-0100