SH7265 Datasheet, PDF (1260/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.9 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)
CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer
memory and writing data to the FIFO buffer memory.
The transmission/reception buffer memory of this module has a FIFO structure (FIFO buffer). Use
the FIFO port registers to access the FIFO buffer. There are three FIFO ports: the CFIFO, D0FIFO
and D1FIFO ports. Each FIFO port is configured of a port register (CFIFO, D0FIFO, D1FIFO)
that handles reading of data from the buffer memory and writing of data to the FIFO buffer
memory, a select register (CFIFOSEL, D0FIFOSEL, D1FIFOSEL) that is used to select the pipe
assigned to the FIFO port, and a control register (CFIFOCTR, D0FIFOCTR, D1FIFOCTR).
These registers are initialized by a power-on reset.
Bit: 31
Initial value: 0
R/W: R/W
30
0
R/W
29
0
R/W
28
0
R/W
27
0
R/W
26
0
R/W
25 24 23 22
FIFOPORT[31:16]
0
0
0
0
R/W R/W R/W R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
8
7
6
FIFOPORT[15:0]
0
0
0
0
R/W R/W R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
31 to 0
Initial
Bit Name Value
R/W
FIFOPORT H'00000000 R/W
[31:0]
Description
FIFO Port
Accessing these bits allow reading the received data
from the buffer memory or writing the transmit data to
the buffer memory.
Rev. 1.00 Mar. 14, 2008 Page 1224 of 1984
REJ09B0351-0100