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| SH7265 Datasheet, PDF (1133/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 21 IEBusTM Controller (IEB)
21.6.3 Master Receive Operation
Figure 21.15 shows the timing for master receive operation.
IECMR
IEFLG
CMX
MRQ
SRQ
Slave
reception
DL
Dn-1 Dn
Master
reception
HD MA SA CT DL D1 D2
Master transmission request
SRE
IERSR
RXS
RXF
[Legend]
HD: Header
MA: Master address field
SA: Slave address field
CT: Control field
DL: Message length field
Dn: Data field
Figure 21.15 Master Receive Operation Timing
Dn-1 Dn
Rev. 1.00 Mar. 14, 2008 Page 1097 of 1984
REJ09B0351-0100
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