SH7265 Datasheet, PDF (209/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 Interrupt Controller (INTC)
Table 7.5 Interrupt Request Sources and C0IPR01, C0IPR02, and C0IPR05 to C0IPR21
and C1IPR01, C1IPR02, and C1IPR05 to C0IPR21
Bit
Register
15 to 12
11 to 8
7 to 4
3 to 0
Interrupt priority register 01 IRQ0
IRQ1
IRQ2
IRQ3
Interrupt priority register 02 IRQ4
IRQ5
IRQ6
IRQ7
Interrupt priority register 05 PINT0 to PINT7 Reserved
Reserved
Reserved
Interrupt priority register 06 DMAC0
DMAC1
DMAC2
DMAC3
Interrupt priority register 07 DMAC4
DMAC5
DMAC6
DMAC7
Interrupt priority register 08 DMAC8
DMAC9
DMAC10
DMAC11
Interrupt priority register 09 DMAC12
DMAC13
DMAC-shared USB
Interrupt priority register 10 CMT0
CMT1
CMT2
CMT3
Interrupt priority register 11 WDT0
WDT1
MTU0
MTU0
(TGI0A to TGI0D) (TCI0V, TGI0E,
TGI0F)
Interrupt priority register 12 MTU1
MTU1
MTU2
MTU2
(TGI1A, TGI1B) (TCI1V, TCI1U) (TGI2A, TGI2B) (TCI2V, TCI2U)
Interrupt priority register 13 MTU3
MTU3
(TGI3A to TGI3D) (TCI3V)
MTU4
MTU4
(TGI4A to TGI4D) (TCI4V)
Interrupt priority register 14 SSIF0
SSIF1
SSIF2
SSIF3
Interrupt priority register 15 SSIF4
SSIF5
AESOP
Reserved
Interrupt priority register 16 IIC3_0
IIC3_1
IIC3_2
IIC3_3
Interrupt priority register 17 SCIF0
SCIF1
SCIF2
SCIF3
Interrupt priority register 18 SCIF4
SCIF5
Reserved
Reserved
Interrupt priority register 19 SSU0
SSU1
ADC
2DG
Interrupt priority register 20 ATAPI
FLCTL
RTC
SDHI
Interrupt priority register 21 RCAN0
RCAN1
IEB
Reserved
As shown in table 7.5, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set.
Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the
highest level).
Rev. 1.00 Mar. 14, 2008 Page 173 of 1984
REJ09B0351-0100