SH7265 Datasheet, PDF (14/2024 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus State Controller (BSC) ............................................................. 265
10.1 Features............................................................................................................................. 265
10.2 Input/Output Pins.............................................................................................................. 267
10.3 Area Overview.................................................................................................................. 269
10.3.1 Address Map..................................................................................................... 269
10.3.2 Data Bus Width and Pin Function Setting for Individual Areas ....................... 271
10.4 Register Descriptions........................................................................................................ 272
10.4.1 CSn Control Register (CSnCNT) (n = 0 to 5)................................................... 274
10.4.2 CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 5) ......................... 276
10.4.3 SDRAMCm Control Register (SDCmCNT) (m = 0, 1).................................... 278
10.4.4 CSn Mode Register (CSMODn) (n = 0 to 5) .................................................... 279
10.4.5 CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 5) ................................. 282
10.4.6 CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 5) ................................. 284
10.4.7 SDRAM Refresh Control Register 0 (SDRFCNT0)......................................... 287
10.4.8 SDRAM Refresh Control Register 1 (SDRFCNT1)......................................... 288
10.4.9 SDRAM Initialization Register 0 (SDIR0)....................................................... 290
10.4.10 SDRAM Initialization Register 1 (SDIR1)....................................................... 292
10.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ................................. 293
10.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT)..................... 294
10.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)........................................ 295
10.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ............................................ 297
10.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)........................................... 299
10.4.16 SDRAM Status Register (SDSTR) ................................................................... 300
10.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .............. 302
10.4.18 AC Characteristics Switching Register (ACSWR) ........................................... 303
10.5 Operation .......................................................................................................................... 304
10.5.1 Accessing CS Space.......................................................................................... 304
10.5.2 Accessing SDRAM........................................................................................... 318
10.6 Connection Examples ....................................................................................................... 356
10.7 Usage Notes ...................................................................................................................... 361
10.7.1 Write Buffer...................................................................................................... 361
10.7.2 Point for Caution at the Time of a Transition to Software Standby or
deep Standby Mode........................................................................................... 361
Section 11 Direct Memory Access Controller (DMAC)................................... 363
11.1 Features............................................................................................................................. 363
11.2 Input/Output Pins.............................................................................................................. 366
11.3 Register Descriptions........................................................................................................ 367
11.3.1 DMA Current Source Address Registers (DMCSADRn)................................. 378
Rev. 1.00 Mar. 14, 2008 Page xiv of xxxvi